Memristor-The missing circuit element

TL;DR — In 1971, Leon Chua looked at the four basic circuit variables, noticed that only five of the six possible pairwise relations had a device attached to them, and postulated the sixth: a two-terminal passive element whose resistance is a function of the total charge that has ever flowed through it. No material was known to do this, and at 1971 feature sizes the effect would have been unmeasurably small; at nanometer scales it dominates. Today, resistive-switching devices sit at exactly this intersection, and the payoff Chua couldn't have named — analog, in-memory matrix-vector multiplication, the primitive that eats most of an LLM's energy budget — is the reason this 54-year-old symmetry argument is a live engineering race rather than a historical footnote.

The idea: complete the square

Circuit theory has four fundamental variables: voltage v, current i, charge q = \int i\,dt, and flux linkage \varphi = \int v\,dt. Two of the six pairwise relations are definitions (the integrals above). Three had devices: the resistor relates v and i, the capacitor relates q and v, the inductor relates \varphi and i.

That leaves one relation dangling: \varphi versus q. Chua's move was to take the symmetry seriously and define the device that would fill the hole. If a component is characterized by a curve \varphi = f(q), then differentiating gives

where M(q) has units of ohms. It looks like a resistor, but its resistance depends on the history of charge through it — hence memristor, memory resistor. Cut the current and M freezes at its last value: intrinsic, nonvolatile analog memory in a two-terminal passive element.

Chua didn't stop at the definition. He proved a passivity criterion (M(q) \ge 0 everywhere makes the element passive — it never sources energy), showed that no finite network of resistors, capacitors, and inductors can reproduce memristor behavior (it is genuinely a fourth element, not a composite), demonstrated an active op-amp emulator so the dynamics could be studied on the bench, and sketched applications in signal processing and modeling. What he could not do was point to a material. The paper is explicit that the element is postulated, not discovered — a prediction from symmetry, in the spirit of Mendeleev's gaps or Dirac's positron.

One honest caveat about the framing: the \varphi in the definition is flux linkage, \int v\,dt, a bookkeeping variable — not necessarily magnetic flux threading anything. Critics have made much of this ever since, and it matters for the "was it really found?" debate below.

Why it couldn't work in 1971

Two limits, one physical and one motivational.

The physical one is the killer, and it has a clean scaling law — though it was only articulated in Strukov, Snider, Stewart, and Williams' 2008 Nature paper. In a thin film where conduction is modulated by drifting dopants or ions, the memristive term in the v–i relation scales roughly as 1/D^2, where D is the film thickness: one factor of 1/D because a given charge moves the internal state boundary a larger fraction of a thinner device, and another because fields (hence ion drift rates) are larger at fixed voltage. Circuit-relevant feature sizes in 1971 were around 10 μm; HP's TiO₂ films in 2008 were around 5 nm. That's roughly three orders of magnitude in D, hence roughly six orders of magnitude in the strength of the memristive effect. At micron scales the effect is buried under ordinary resistance and noise; at nanometer scales it is the device. Nobody in 1971 could fabricate, image, or electrically probe a 5 nm functional film.

The motivational limit: even if someone had stumbled onto a resistive-switching material (and in hindsight, scattered reports of hysteretic resistance in oxides go back to the 1960s), there was no reason to want one. Digital logic was ascendant, memory meant cores and soon DRAM, and "analog resistance that drifts with use" reads as a defect, not a feature. The application that makes memristors valuable — dense analog storage of neural network weights, computed on in place — required neural networks to matter, which took another four decades.

What changed

Three things, compounding.

Fabrication. Nanoscale thin-film stacks are routine. Resistive RAM is in foundry PDKs as embedded nonvolatile memory (TSMC and others at 22–28 nm class nodes), phase-change memory shipped commercially (Intel/Micron's 3D XPoint, since discontinued but manufactured at scale), and the crosspoint cell is about as small as a memory cell gets (4F^2 footprint, stackable in 3D).

The 2008 identification. HP's group showed a Pt/TiO₂/Pt nanodevice whose behavior maps onto Chua's equations, exhibiting the pinched hysteresis loop (the v–i curve of a memristor under sinusoidal drive always passes through the origin — the fingerprint Chua and Kang formalized in their 1976 "memristive systems" generalization). This is also where honesty is required: real devices are memristive systems with internal state variables set by ion positions, filament geometry, and temperature — not ideal charge-controlled memristors where state is purely \int i\,dt. A vocal minority (e.g., Vongehr and Meng, 2015) argues the ideal memristor may be physically unrealizable and that "the missing memristor" was never actually found. For engineering purposes the distinction is mostly academic; for the symmetry argument's purity, it's a genuine open question.

The workload. Transformer inference is dominated by matrix-vector products, and at small batch sizes it is memory-bandwidth-bound: the energy goes into moving weights, not multiplying them. (Horowitz's classic numbers: an 8-bit multiply at 45 nm costs roughly 0.2 pJ; a DRAM access costs hundreds of pJ — data movement wins by orders of magnitude.) A memristor crossbar dissolves this: store weight W_{jk} as a conductance G_{jk}, apply input voltages V_j on rows, and Ohm's law plus Kirchhoff's current law deliver I_k = \sum_j G_{jk} V_j on each column — a full matrix-vector multiply in one physical step, with zero weight movement.

A serious 2026 revival

The honest benchmark is joules per token on LLM inference, end to end, including converters — because in every analog demo to date, the ADCs at the column outputs, not the crossbar, dominate energy. Core analog MACs plausibly cost single-digit femtojoules; system-level demonstrations (IBM's 2023 phase-change chip in Nature, Mythic's flash-based analog parts) land around 10 TOPS/W-class efficiency — good, but roughly 10× over digital rather than the 100× the crossbar core promises.

A credible architecture: keep the memristive crossbars for the static, reuse-heavy weights (FFN blocks and attention projections — the bulk of parameters), do attention over the KV cache digitally (it's dynamic, and write endurance of ~10⁶–10⁹ cycles makes memristors terrible for rapidly changing state), and attack the ADC bottleneck with low-precision, charge-domain, or ADC-free readout schemes. Precision is the real fight: device noise, drift, and IR drop across large arrays limit effective precision to roughly 4–6 bits per device, so differential pairs and bit-slicing are mandatory — and conveniently, LLM weight quantization research has spent five years proving 4-bit weights are enough.

What to reuse from Chua's paper, specifically: the intrinsic memory. Conductance updates from overlapping pre/post voltage pulses implement local, Hebbian-flavored plasticity in the physics, with no weight fetch and no backward pass through memory. A 2026 revival worth the name pairs frozen crossbar inference with a local adaptation rule — equilibrium propagation, feedback alignment, or IBM's Tiki-Taka-style schemes that tolerate the asymmetric, nonlinear conductance updates that wreck naive SGD — for on-chip fine-tuning and continual adaptation at the edge.

Tried, vindicated, still open

Substantially tried, partially vindicated, unwon. The element exists (modulo the ideal-vs-memristive-system dispute) and Chua's symmetry prediction is one of the cleanest in circuit theory. Crossbar inference works at research scale: Prezioso et al. trained a small memristor network in situ (2015); Yao et al. ran a fully hardware memristor CNN (Nature, 2020); IBM's analog chips run real speech and language workloads; a Tsinghua group demonstrated a fully analog photonic-electronic pipeline. HP's own memristor-memory ambitions ("The Machine") quietly shipped without memristors, a useful cautionary tale.

Still open: closing the gap between femtojoule cores and system-level joules (the ADC problem); scaling from millions of devices to the tens of billions an LLM needs, almost certainly via 3D stacking; drift compensation over months; and whether any local learning rule delivers competitive quality on modern architectures. Also genuinely open, and charming: whether an ideal passive memristor — Chua's actual element, state a pure function of charge — exists in nature at all.

Where to read it

The paper is at doi.org/10.1109/tct.1971.1083337 (bibliographic details verified). Read it alongside Chua & Kang, "Memristive devices and systems" (Proc. IEEE, 1976), which defines the class real devices actually belong to; Strukov et al., "The missing memristor found" (Nature, 2008), for the 1/D^2 argument that explains the 37-year gap; and, for the modern engineering picture, any recent review of analog in-memory computing for deep learning (the IBM Zurich group's surveys are a good entry point). For the skeptical counterweight, Vongehr & Meng's "The missing memristor has not been found" (2015) is the sharpest statement of the case that the square, strictly speaking, is still open.